1. Field of the Invention:
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having a voltage generator generating an internal power voltage lower than an externally applied power voltage.
2. Description of the Related Art:
Integration scale of semiconductor integrated circuits has been increased by reducing sizes of circuit elements such as transistors formed therein. As a result of such reduction in sizes of circuit elements, large scale integrated circuits have been realized. For example, for reducing the sizes of MOS field effect transistors, the channel length of MOS transistors has been particularly reduced. In specifically, in the recently announced proto-type 4M-bit DRAMs, MOS transistors having channel length of 1 micron or less were employed.
However, if MOS transistors having such short channel length as 1 micron or less are driven by such high power voltage as the conventional power voltage of 5 volts, the characteristics of the short-channel MOS transistors are likely to be degraded due to hot carriers, resulting in a lowered withstanding voltage. For avoiding the above degradation, it is desirable to drive the short-channel MOS transistors with a lower power voltage than the conventional power voltage (5 volts). From a view point of interface with system outside DRAMs and simplification of power voltage source, however, it is still advantageous to employ the conventional power voltage.
Under the above circumstance, it has been proposed to provide in a semiconductor chip a voltage generator generating an internal power voltage lower than 5 volts used in the conventional power system for driving the reduced-size circuit elements. By the proposed, while the unification of the power voltage with peripheral system is kept, the problem due to the short-channel MOS transistors was solved.
However, current driving ability is also reduced by driving the short-channel MOS transistors with the lower internal power voltage. A clock generator or a delay circuit for producing clocks which is combined in the same chip cannot supply clocks having sufficient current. As a result, switching characteristics, particularly, switching time of the short-channel MOS transistors used for signal processing become unstable. This unstability of the switching characteristics causes another serious problem in a timing signal generator circuit or a delay signal generator circuit which is composed of the reduced-size MOS transistors driven by the internal voltage.
Namely, it is an essential matter in the timing signal generator that current values of currents flowing through a transistor for feeding the power voltage and through a transistor for feeding the ground voltage in a unit of inverters forming the timing signal generator and a ratio of the current values flowing through the above transistors are important parameters to determine a delay or response time of the unit of inverter. However, the reduced-size transistors driven by the internal power voltage cannot produce an accurate amount of current as designed and it is difficult to establish a predetermined ratio between the currents flowing through each of the two transistors forming the inverter.
In other words, fluctuations in current values and ratio of currents flowing through a plurality of transistors are large in those transistors driven by the internal power voltage.
Thus, timing signals generated from the timing signal generator driven by the internal power voltage fail to have an accurate time relationship therebetween. Therefore, it is difficult to regulate operations of a functional circuit accurately by the timing signals generated by the above timing signal generator.